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Guild: wafer.space Community
Channel: 📐 - Designing / 📝-project-template / Template update
After: 2026-06-30 11:59 p.m.
Before: 2026-08-01 12:00 a.m.
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[2026-07-14 1:23 p.m.] rebelmike



[2026-07-14 1:23 p.m.] rebelmike
Awesome, thanks Leo - that makes the update nice and easy to apply 🙂

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[2026-07-14 2:02 p.m.] namibj
Notably, the `buf_8` (and the identical in all ways that matter, `clkbuf_8`) had a gate finger (spanning both pmos and nmos) in place of what probably should have been a diffusion break; result was that the 3 active fingers on the input (depends on if high or low; the cell is electrically symmetric between nmos and pmos) fed a diode-connected finger of the 8 output fingers (they all share the same gate) and e.g. on input low resulted in about 2.7V (TT default temperature) across an nmos finger with a little over 300μA through that finger; a side effect should be that the actual output fingers don't properly turn their complement (in that condition, the pmos fingers) off at least on some PVT corners, which causes further but probably overall less significant power dissipation.

TL;DR: an accidentally placed gate in `buf_8` and `clkbuf_8` caused 1 mW static power consumption (and possibly somewhat impaired output logic levels, I'd particularly worry about reduced output-high levels).

Many chips would probably just "melt" from the power wastage.


[2026-07-14 5:31 p.m.] rtimothyedwards_19428
Fortunately on my SRAM test chip I went for a `buf_12`.  But I expect that my original SoC design on Run 1 is toast (or is a toaster).

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[2026-07-14 6:22 p.m.] namibj
I'll try to simulate the old broken buffer behavior on very low supply voltage around next week or thereabouts; there's a chance it's operable at least if you don't have any deliberate power gating transistors in your design that would rely on sufficiently strong gate drive for sufficiently tame voltage drop.


[2026-07-15 8:37 p.m.] rtimothyedwards_19428
Well, I did a count of the `buff_8` on `gf180mcu_ocd_openframe` (my PicoRV32 test chip with all 3.3V components) and it uses `buff_8` 2,498 times, so that is potentially a lot of current.


[2026-07-15 8:42 p.m.] rtimothyedwards_19428
I assume that the buffer is _functional_ or else `lctime` would have produced garbage output in the .lib file for it.  The amount of current is going to be the issue.  I estimate somewhere between a half an amp and an amp total.


[2026-07-15 8:54 p.m.] namibj
It does _buffer,_ on tt 3v3 default spice temperature it has an output high of like 2.71 V.


[2026-07-15 8:57 p.m.] namibj
The pertinent question will be how the STA holds up as you drop voltage and clock.
Does it reach a point where it won't try to melt the die (2.5W is "manageable") and still doesn't experience hold violations?


[2026-07-15 8:58 p.m.] namibj
(I'm thinking that maybe at like 1.2V or something the static power stops needing a heatsink and the chip can run at still like 1% nominal clock speed or such.)


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